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[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] fifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8 * 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1072 | Author: 夏社 | Hits:

[Other resource] vhdl_fifo

Description: 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
Platform: | Size: 309997 | Author: 蔡庆重 | Hits:

[Other resource] FIFO

Description: VHDL源代码程序，使用VHDL语言编写，一个FIFO的代码实现工程
Platform: | Size: 3751 | Author: 罗兰 | Hits:

[Other resource] FIFO

Description: FIFO的源代码，对FIFO设计有帮助，有借鉴意义，帮助学习VHDL编程
Platform: | Size: 908 | Author: 胡清泉 | Hits:

[Other resource] fifo-1117

Description: 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好
Platform: | Size: 20434 | Author: 杨宇 | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[Other resource] fifo

Description: 使用VHDL编程的异步FIFO程序 经调试可运行
Platform: | Size: 131086 | Author: 张星 | Hits:

[Other resource] VHDL

Description: 高质量的VHDL代码乒乓处理FIFO缓存
Platform: | Size: 915 | Author: wode | Hits:

[Other resource] FIFO

Description: 用VHDL语言编写的实现FIFO的设计，经编译下载成功
Platform: | Size: 67226 | Author: henry | Hits:

[Other resource] RS232uart(VHDL)

Description: 256字节深度的RS232串口程序,共分4个模块,顶层文件\\FIFO程序\\串口收和串口发.经过测试已用于产品.可靠!
Platform: | Size: 5377 | Author: 温海龙 | Hits:

[Windows Develop] fifo源程序

Description: fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
Platform: | Size: 1136 | Author: 许 | Hits:

[VHDL-FPGA-Verilog] uart from opencores

Description: 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Platform: | Size: 9216 | Author: 熊明 | Hits:

[VHDL-FPGA-Verilog] EPP

Description: 并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
Platform: | Size: 1024 | Author: 陈刚 | Hits:

[VHDL-FPGA-Verilog] vhdl-fifo

Description: vhdl 语言实现fifo功能模块 包含接口：clk、data_in、data_out-fifo use vhdl
Platform: | Size: 1024 | Author: 张树强 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
Platform: | Size: 4096 | Author: 刀刀 | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[File Format] FIFO

Description: FIFO verilog VHDL-FIFO verilog VHDL
Platform: | Size: 52224 | Author: 徐云川 | Hits:

[Other] FIFO

Description: FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
Platform: | Size: 67584 | Author: sam | Hits:

[VHDL-FPGA-Verilog] uut_3

Description: VHDL设计的FIFO 经典结构 功能详尽 敬请参阅(VHDL designed FIFO classic structure functions in detail please refer to)
Platform: | Size: 839680 | Author: 名之联 | Hits:
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